Static Timing Analysis Jobs In - 36 Job Positions Available

We are looking for motivated engineers with Static timing analysis skill; good knowledge on timing convergence and corner definition in advanced tech nodes. If you have expertise in this area and are excited by driving leading edge semiconductor technologies those

We are looking for motivated engineers with Static timing analysis skill; good knowledge on timing convergence and corner definition in advanced tech nodes.If you have expertise in this area and are excited by driving leading edge semiconductor technologies that make

Link-Worldwide is seeking a motivated ASIC Timing Analysis Engineer in Tijuana, Mexico. This role involves driving advanced semiconductor technologies, focusing on timing analysis and closure in complex processes from 40nm to 3nm.The ideal candidate should have strong skills in static timing analysis, programming

Qualifications Master’s degree or higher in electrical engineering. Expertise in static timing analysis. Strong coding skills in languages such as Python, TCL, Perl. Strong methodology development background. Strong analysis and communication skills. Helpful Experience Familiarity with Ansys Redhawk/RHSC and PDN

Overview: We Are PepsiCo Join PepsiCo and dare to transform! We are the perfect place for curious people, thinkers and change agents.From leadership to front lines, were excited about the future and working together to make

The candidate will work closely with the San Diego DTech (Design Technology) methodology team. The candidate will help to develop static timing analysis and power/timing optimization methodologies, will work with vendors such as Synopsys and Cadence to define and validate

Qualifications. :- Masters degree or higher in electrical engineering. - Expertise in static timing analysis. - Strong coding skills in languages such as Python, TCL, Perl. - Strong methodology development background. - Strong analysis and communication skills. Helpful Experience. :-

Project description : Our client was built on the belief that freedom of movement drives human progress. As we look to the future and the changing needs of society, our client is committed to becoming the

The Physical Design Engineer (EM/IR Closure Engineer) is a hands‐on individual contributor responsible for block‐level and subsystem‐level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close collaboration

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver

Company QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area Engineering Group, Engineering Group ASICS Engineering Role Overview About the Role As a member of the methodology/PPA team, you will work closely with various core

Frontier of On-device AI Semiconductors for Everyone, Everywhere. Deep X Co., Ltd. DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era. By delivering the world’s most energy-efficient NPU technology, we

Job Description The Physical Design Engineer (EM/IR Closure Engineer) is a hands‑on individual contributor responsible for block‑level and subsystem‑level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and

North American Production Sharing de México, S.A. de C.V. is seeking a candidate to develop methodologies for static timing analysis and power/timing optimization. The role involves close collaboration with the San Diego DTech team and support for design teams with

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver