This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the
We are looking for motivated engineers with Static timing analysis skill; good knowledge on timing convergence and corner definition in advanced tech nodes. If you have expertise in this area and are excited by driving leading edge semiconductor technologies those
Job Details: Job Description: As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs at Intel. Your work will directly influence the cutting-edge technology
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: About the Role Required Qualifications and Skills B.S/M.S. degree in Electrical Engineering, Computer Science. 1-2 years of experience in
SOFTWARE PROJECT MANAGER - HYBRIDLocation Tlaquepaque, Mexico Pacesetting. Passionate. Together. FORVIA HELLA is a listed international automotive supplier. As a company of the FORVIA Group, FORVIA HELLA stands for high-performance lighting technology and vehicle electronics and,
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: We are looking for talented and ambitious individuals to join the TECHIP team. The candidate should have strong IP
ResponsibilitiesDesign, release, and integrate seat structure components and assemblies, including Front and rear seat structures, Seat tracks, Recliners, Manual and power adjusters, Latchesand fold-flat mechanisms, Structural brackets and mounting systems, Welded assemblies, Stampings and tubular structures,
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
North American Production Sharing de México, S.A. de C.V. is seeking a candidate to develop methodologies for static timing analysis and power/timing optimization. The role involves close collaboration with the San Diego DTech team and support for design teams with
Responsibilities Design, release, and integrate seat structure components and assemblies, including Front and rear seat structures, Seat tracks, Recliners, Manual and power adjusters, Latchesand fold-flat mechanisms, Structural brackets and mounting systems, Welded assemblies, Stampings and tubular
Our vision is to transform how the world uses information to enrich life for _all_ . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence,
Company QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area Engineering Group, Engineering Group ASICS Engineering Role Overview About the Role As a member of the methodology/PPA team, you will work closely with various core
SOFTWARE PROJECT MANAGER - HYBRID Location Tlaquepaque, Mexico Pacesetting. Passionate. Together. HELLA is a listed, internationally positioned automotive supplier operating under the umbrella brand FORVIA. Within this de facto group, HELLA stands for high-performance lighting technology
SOFTWARE PROJECT MANAGER - BODY (HYBRID) Location Tlaquepaque, Mexico Pacesetting. Passionate. Together. HELLA is a listed, internationally positioned automotive supplier operating under the umbrella brand FORVIA. Within this de facto group, HELLA stands for high-performance lighting
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
Job Details Job Description: As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs at Intel. Your work will directly influence the cutting‑edge technology
The candidate will work closely with the San Diego DTech (Design Technology) methodology team. The candidate will help to develop static timing analysis and power/timing optimization methodologies, will work with vendors such as Synopsys and Cadence to define and validate
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
Company :QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area :Engineering Group, Engineering Group ASICS Engineering General Summary : About the Role Required Qualifications and Skills - B.S/M.S. degree in Electrical Engineering, Computer Science. -