Job Details: Job Description: The Physical Design Engineer (EM/IR Closure Engineer) is a hands-on individual contributor responsible for block-level and subsystem-level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication and
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: The RF Product Development and Test Engineering group develops test solutions for design verification and characterization of highly integrated RF
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of RTL2GDS solutions for the Snapdragon chips powering billions
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: The RF Product Development and Test Engineering group develops test solutions for design verification and characterization of highly integrated RF
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: The RF Product Development and Test Engineering group develops test solutions for design verification and characterization of highly integrated RF
North American Production Sharing de México, S.A. de C.V. is looking for an ASIC Engineer in Tijuana. The successful candidate will define and implement IP development for high-performance products. In this role, youll work on the Physical Design Flow, involving
Link-Worldwide in Tijuana, Baja California, is seeking an ASIC Engineer to enhance product development through advanced modeling, design, and verification. This role involves working on the Physical Design Flow of high-speed, low-power designs including GPU and Modem. The ideal candidate will have
As a leading technology innovator, we push the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a ASIC Engineer, you will
As an ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Engineers collaborate with cross-functional groups to
Frontier of On-device AI Semiconductors for Everyone, Everywhere.DeepX Co., Ltd. DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.By delivering the worlds most energy-efficient NPU technology, we are solving the critical
Frontier of On-device AI Semiconductors for Everyone, Everywhere. Deep X Co., Ltd. DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era. By delivering the worlds most energy-efficient NPU technology, we are
ASIC/Layout Design Engineer 1 Position Summary :The ASIC/Layout Design Engineer 1 position is responsible for performing basic physical design and layout activities within our semiconductor company. This position supports ASIC layout development, assists with physical verification, and helps implement design components. The role requires fundamental understanding of
Job Details:Job Description:The Physical Design Engineer (EM/IR Closure Engineer) is a hands-on individual contributor responsible for block-level and subsystem-level EM/IR analysis and closure.The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close collaboration with Physical Design, STA,
We Are : At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in
Job Description The Physical Design Engineer (EM/IR Closure Engineer) is a hands‑on individual contributor responsible for block‑level and subsystem‑level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close collaboration with
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors. Responsibilities
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors. Responsibilities
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors. Responsibilities
CompanyQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob AreaEngineering Group, Engineering Group ASICS EngineeringGeneral SummaryAs a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT marketsResponsibilitiesThe candidate will work