Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Senior Test Engineer must have the ability to be part of a focused, high-energy team that
Req ID 87880 | MSSC Guadalupe, Mexico, ZF ENGINEERING AND SHARED SERVICES MONTERREY, S DE RL DE CV Job Description About the Team ZF is looking to hire a HW Electronics Engineer II to join our team
Intel Corporation is looking for an Atom CPU Layout Design Engineer in Guadalajara, Mexico. The ideal candidate should have a Bachelors degree in Electrical or Computer Engineering and at least 2 years of layout design experience. This role includes
RDT Ingenieros es una empresa innovadora cuyo ámbito de actuación es el desarrollo de proyectos de ingeniería avanzados, participando en proyectos de alto componente tecnológico de grandes clientes. Solicita :*ASIC verifier and tester Actualmente estamos buscando un
BairesDev is seeking an RTL Design Engineer to design register-transfer-level logic for ASIC chips. In this remote position, you will develop complex RTL modules using Verilog and SystemVerilog, translating architectural requirements into robust designs. Candidates should have over 4 years of
Qualcomm is seeking an ASIC Engineer in Tijuana, Baja California, to drive innovations in digital and analog design. This role involves defining and optimizing IP development for high-performance products, requiring collaboration with cross-functional teams to meet system requirements. Candidates
North American Production Sharing de México, S.A. de C.V. is looking for an ASIC Engineer in Tijuana. The successful candidate will define and implement IP development for high-performance products. In this role, youll work on the Physical Design Flow,
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob Area:Engineering Group, Engineering Group ASICS EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation
Qualcomm in Tijuana is seeking an experienced ASIC Engineer to lead the design and validation of low power integrated circuits. The ideal candidate should have a Bachelors or Masters degree in Engineering and at least 2 years of relevant
ASIC/Layout Design Engineer 1Position Summary: The ASIC/Layout Design Engineer 1 position is responsible for performing basic physical design and layout activities withinour semiconductor company.This position supports ASIC layout development, assists with physical verification, and helps implement design components.The role requires fundamental understanding of semiconductor layout
Intel Corporation is seeking a Layout Design Intern in Guadalajara, Mexico. The role is focused on contributing to semiconductor development, supporting layout implementation, and collaborating with senior engineers. Candidates should be pursuing a Bachelors or Masters degree in
In this position, you will be responsible for the design and development of complex printed circuit boards and/or subsystems for Intel architecture server platforms for validation of enterprise processors and chipset. Your responsibilities will include but not
Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area: Engineering Group, Engineering Group ASICS Engineering General Summary Qualcomm is a company of inventors that deliver leading-edge AI, high performance, lower-power computing, and unrivaled connectivity. It
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient