At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our
Job Details: Job Description: The Physical Design Engineer (EM/IR Closure Engineer) is a hands-on individual contributor responsible for block-level and subsystem-level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for
Digital Design & Verification Engineer NAPS is supporting a leading global semiconductor company in the search for talented Digital Design and Digital Verification Engineers to join a highly technical and development‑driven team. This is an excellent
Your role Design, develop, and maintain high-quality APIs and microservices, ensuring scalability, security, and stability in production environments, primarily in banking projects. Design and develop REST APIs and microservices using Java and modern frameworks. Translate functional
Job Overview This position requires candidates to upload a resume in English; multiple versions may be submitted, but at least one English version is required to be considered for this position. We are looking for a
A technology startup in Guadalajara, Mexico is looking for a Physical Design Engineer to optimize CPU power, performance, and area (PPA). The role involves physical implementation from RTL-to-GDSII, working closely with RTL designers to enhance efficiency.
Support emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware, bootloaders,
The candidate will work closely with the San Diego DTech (Design Technology) methodology team. The candidate will help to develop static timing analysis and power/timing optimization methodologies, will work with vendors such as Synopsys and Cadence to
Link-Worldwide, a leader in technology solutions based in Mexico, is seeking a candidate to drive innovation in chip design. You will engage with customers using Synopsys tools like RTL Architect and Fusion Compiler. A strong technical background and
This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the
ESSS está en busca de un Analista de Marketing Pleno para fortalecer nuestra presencia en México, apoyando estrategias de generación de demanda, eventos e inbound marketing en colaboración con el equipo comercial. Buscamos un profesional organizado,
49669BR - MEXICO - Guadalajara Job Description and Requirements - We’re not just a traditional EDA & IP company you’re familiar with. We understand how the SoCs we help create are used, and work with our
# Welcome! # .# Job Details: # Job Description:This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and
# Welcome! # .# Job Details: # Job Description:This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of
ESSS está en busca de un Analista de Negocios para fortalecer nuestra presencia en América Latina. Buscamos un profesional organizado, proactivo y orientado a resultados, con experiência en ventas de software y negociación, capaz de contribuir
We are seeking a highly motivated and experienced Senior CPU Pre‑Silicon Verification Engineer to join our advanced CPU verification team. The role focuses on ensuring the functional correctness and robustness of CPU logic designs through state‑of‑the‑art
Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
As an ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Engineers collaborate