We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
A technology startup in Guadalajara, Mexico is looking for a Physical Design Engineer to optimize CPU power, performance, and area (PPA). The role involves physical implementation from RTL-to-GDSII, working closely with RTL designers to enhance efficiency.
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
The candidate will work closely with the San Diego DTech (Design Technology) methodology team. The candidate will help to develop static timing analysis and power/timing optimization methodologies, will work with vendors such as Synopsys and Cadence to
Role open in France, Spain or Greece We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to
Instructor in Semiconductors Overview About the Role - Participation in live classes every Wednesday from 1:00 p.m. to 2:00 p.m. (CDMX time) . - Collaboration period :May 14 to September 24, . - Availability starting Monday,
We are seeking a hands‑on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. The role includes ownership of verification planning, UVM testbench development, test content creation, coverage closure, and debugging across block, subsystem,
We Are :At Synopsys, we drive the innovations that shape the way we live and connect.Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.We lead in chip design, verification, and
As a leading technology innovator, we push the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a ASIC Engineer,
Link-Worldwide, a technology startup located in Guadalajara, Mexico, is seeking a Physical Design Engineer to optimize CPU power, performance, and area (PPA). The role involves physical design implementation from RTL to GDSII, requiring collaboration with RTL
We Are : At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip
Category Engineering Hire Type Employee Job ID *Date Posted 20/08/2025 *: We Are : At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive
# Welcome! # . # Job Details: # Job Description:This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version
Job Details : As a Senior Layout Design Engineer within the DTP AMS group, you will play a pivotal role in delivering best-in-class IO IPs on leading-edge process nodes. You will work at the intersection of
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and