Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring
Job Details Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
Support emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware, bootloaders,
# Welcome! #.# Job Details: # Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
Responsibilities Lead emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware,
Intel Corporation in Guadalajara, Mexico is seeking a hands-on Physical Design Engineer (EM/IR Closure) to own block-level reliability closure and drive EM/IR signoff within SAM frameworks, collaborating with Physical Design, STA and Methodology teams.The role requires
Job Details : Were looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and
Job Description and Requirements At Synopsys, were at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. And were powering it all
We Are ¿Tiene su CV preparado? Si es así y confía en que este es el puesto ideal para usted, asegúrese de enviar su solicitud lo antes posible. Synopsys is the leader in engineering solutions from silicon
Bachelors degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Masters degree in Science, Engineering, or related field and 3+ years of ASIC design,
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with
The Physical Design Engineer (EM/IR Closure Engineer) is a hands‐on individual contributor responsible for block‐level and subsystem‐level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close
Req ID: JR DRAM Layout engineer (Intern)Our vision is to transform how the world uses information to enrich life for all.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation
A technology startup in Guadalajara, Mexico is looking for a Physical Design Engineer to optimize CPU power, performance, and area (PPA). The role involves physical implementation from RTL-to-GDSII, working closely with RTL designers to enhance efficiency.Candidates
Job Overview This position requires candidates to upload a resume in English; multiple versions may be submitted, but at least one English version is required to be considered for this position. We are looking for a
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes.You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance,
We are seeking a highly motivated and experienced Senior CPU Pre‑Silicon Verification Engineer to join our advanced CPU verification team. The role focuses on ensuring the functional correctness and robustness of CPU logic designs through state‑of‑the‑art