Job Details: Job Description: We are seeking a passionate and driven professional with a strong interest in building emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Please consider that this is
About The Opportunity We are building a rigorous, verifiable evaluation suite of Terminal-Bench tasks designed to test the limits of large language models on multilingual software challenges. Our goal is to measure multilingual robustness across prompt
GMV is expanding its GNSS-User Segment Navigation team in Castilla-La Mancha, Spain. Revise detenidamente toda la documentación de la solicitud antes de hacer clic en el botón de solicitar al final de esta descripción. You will
QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA is seeking an ASIC engineer to contribute to RTL design, verification, and integration for sub‐5nm SoCs in mobile, AI, and XR spaces. You will work within a fast-paced team on architecture
Intel in Guadalajara, Mexico, seeks a Physical Design Engineer to drive RTL-to-GDS implementation for custom IP and SoC designs. You will execute end-to-end physical design flows, including synthesis, floor planning, placement, routing, and timing closure, while optimizing power, performance, and area.
North American Production Sharing, Inc. seeks an experienced ASIC engineer in Tijuana to join a fast-paced SoC team working on RTL design, verification and high-performance ASIC development for sub-5nm nodes.Ideal candidates have 5-10 years in ASIC design with strong scripting
Job Details : Were looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across
# Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA # Job Area: Engineering Group, Engineering Group \u003e ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\u s possible to
Intel is seeking a passionate hardware verification professional to build emulation and FPGA models from RTL design, using synthesis, partitioning, and routing tools. This 2-year contract role is based in Guadalajara and supports pre- and post-silicon validation and
Company :QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area :Engineering Group, Engineering Group ASICS Engineering General Summary : Minimum Qualifications : - Bachelors degree in Science, Engineering, or related field. Responsibilities : - Collaborate
The Physical Design Engineer (EM/IR Closure Engineer) is a hands‐on individual contributor responsible for block‐level and subsystem‐level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close collaboration with Physical
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors.Responsibilities-
Job OverviewThis position requires candidates to upload a resume in English; multiple versions may be submitted, but at least one English version is required to be considered for this position. We are looking for a hands‐on
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors.
This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the market.
North American Production Sharing, Inc. is seeking a skilled engineer to design adaptive power management controllers, on-chip sensor controllers, and digital power meters for advanced semiconductor SoCs. You will perform RTL design, simulations, timing analysis, and formal verification, collaborating closely
Job Details Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
As a leading technology innovator, we pushes the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The worlds largest fabless
The Company in Tijuana is seeking an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, low power products. You will collaborate with RTL, DFT, Synthesis and
Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area: Engineering Group, Engineering Group ASICS Engineering General Summary: We are seeking motivated Engineer and Senior Engineer candidates to join our Pre‑Silicon and Post‑Silicon SoC Verification team. In