Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: About the Role Required Qualifications and Skills B.S/M.S. degree in Electrical Engineering, Computer Science. 1-2 years of experience in related
Job Details: Job Description: The Physical Design Engineer (EM/IR Closure Engineer) is a hands-on individual contributor responsible for block-level and subsystem-level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and
Req ID 88779 | MSSC Guadalupe, Mexico, ZF ENGINEERING AND SHARED SERVICES MONTERREY, S DE RL DE CV Job Description About the Team ZF is looking to hire a HW Electronics Engineer II to join our team
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: The RF Product Development and Test Engineering group develops test solutions for design verification and characterization of highly integrated RF
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of RTL2GDS solutions for the Snapdragon chips powering billions
Link-Worldwide in Santiago de Querétaro is looking for an Electrical Engineer to lead custom logic development for aerospace systems. You will be responsible for ensuring design readiness and mentoring early-career engineers. The ideal candidate has a degree in Electrical
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Join Qualcomm Technologies Inc GPU Compiler team to develop software solutions for the world class GPU products. Adreno GPU has
Link-Worldwide in Tijuana, Baja California, is seeking an ASIC Engineer to enhance product development through advanced modeling, design, and verification. This role involves working on the Physical Design Flow of high-speed, low-power designs including GPU and Modem. The ideal candidate will
Link-Worldwide in Mexico, Estado de México is looking for an ASIC/Layout Design Engineer 1 to support physical design and layout activities. This role includes responsibilities in layout support, physical verification, and tool assistance within the semiconductor industry. The ideal candidate
Link-Worldwide in Tijuana, Baja California, is seeking an ASIC Engineer to enhance product development through advanced modeling and verification.This role involves working on high-speed, low-power designs including GPU and Modem.The ideal candidate will possess a Bachelors or Masters in
North American Production Sharing de México, S.A. de C.V. is looking for an ASIC Engineer in Tijuana. The successful candidate will define and implement IP development for high-performance products. In this role, youll work on the Physical Design Flow,
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient
Job Title: Integrated Circuit Package Design Engineer Job Description We are seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing
Job Title: Integrated Circuit Package Design Engineer Job Description We are seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R...
CompanyQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob AreaEngineering Group, Engineering Group ASICS EngineeringGeneral SummaryAs a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT marketsResponsibilitiesThe candidate will work