Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Job Overview We are seeking motivated Engineer and Senior Engineer candidates to join our Pre-Silicon and Post-Silicon SoC Verification
Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: We are seeking motivated Engineer and Senior Engineer candidates to join our Pre-Silicon and Post-Silicon SoC Verification team. In
Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to
We are seeking a CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You will
# Welcome! # .# Job Details: # Job Description:This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of
Company :QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area :Engineering Group, Engineering Group ASICS Engineering General Summary : Job Overview Key Responsibilities - Pre-Si and Post-Si Verification: - Develop and execute verification plans for
Job Details : The SoC Functional Validation Engineer is responsible for defining, developing, and performing functional validation for integrated Systems‑on‑Chip (SoCs). The role focuses on validating IP integrations, interactions between multiple IP blocks, and system‑level features
Responsibilities Lead emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware,
Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
We are seeking a highly motivated and experienced Senior CPU Pre‑Silicon Verification Engineer to join our advanced CPU verification team. The role focuses on ensuring the functional correctness and robustness of CPU logic designs through state‑of‑the‑art
We are seeking a Senior CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You
# Welcome! #.# Job Details: # Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of
Job Overview This position requires candidates to upload a resume in English; multiple versions may be submitted, but at least one English version is required to be considered for this position. We are looking for a
Location: - Queretaro - Queretaro, Mexico - Av. La Noria 170 - Job Family: - Engineering - Worker Type Reference: - Regular - Permanent - Pay Rate Type: - Salary - Career Level: - T3 -
Support emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware, bootloaders,