We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
Our vision is to transform how the world uses information to enrich life for _all_ . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence,
Our vision is to transform how the world uses information to enrich life for _all_ . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence,
We are looking for motivated engineers with Static timing analysis skill; good knowledge on timing convergence and corner definition in advanced tech nodes. If you have expertise in this area and are excited by driving leading
The Physical Design Engineer (EM/IR Closure Engineer) is a hands‑on individual contributor responsible for block‑level and subsystem‑level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close
B.S/M.S. degree in Electrical Engineering, Computer Science. 1-2 years of experience in related fields. Strong programming skills in Python Hands-on experience with static timing analysis (STA) tools, e.g., PrimeTime and Tempus Experience with place & route tools
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
The candidate will work closely with the San Diego DTech (Design Technology) methodology team. The candidate will help to develop static timing analysis and power/timing optimization methodologies, will work with vendors such as Synopsys and Cadence
North American Production Sharing de México, S.A. de C.V. is seeking a candidate to develop methodologies for static timing analysis and power/timing optimization. The role involves close collaboration with the San Diego DTech team and support
The Physical Design Engineer drives integration of analog and mixed signal IPs and highspeed interfaces into subsystems or analog components and partners with package and platform teams on analog integration. Supports pathfinding studies in silicon development