Synopsys Trabajos En Jal - 78 Job Positions Available

Job Details Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver

# Welcome! # .# Job Details: # Job Description:This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of

Support emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware, bootloaders,

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver

Responsibilities Lead emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware,

The Physical Design Engineer (EM/IR Closure Engineer) is a hands‐on individual contributor responsible for block‐level and subsystem‐level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close

At Synopsys, we are at the heart of innovation that changes the way we work and play. Self-driving cars. Artificial Intelligence. The Cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart

We are seeking a motivated and passionate Staff Network Security Engineer interested in joining our global network infrastructure support team responsible for designing, implementing, and maintaining a highly redundant and scalable secure network. You will also

About the Team We are a dynamic technology team that provides exceptional customer service to Synopsys employees across the United States, Canada, Mexico, and Chile. Our team is responsible for the logistics and support of all end-user

We Are : At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip

We Are : At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip

Intel Corporation in Guadalajara, Mexico is seeking a hands-on Physical Design Engineer (EM/IR Closure) to own block-level reliability closure and drive EM/IR signoff within SAM frameworks, collaborating with Physical Design, STA and Methodology teams.The role requires

We Are : At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip

Job Description and Requirements At Synopsys, were at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. And were powering it all

We Are : At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip

We are seeking a highly motivated and experienced Senior CPU Pre‑Silicon Verification Engineer to join our advanced CPU verification team. The role focuses on ensuring the functional correctness and robustness of CPU logic designs through state‑of‑the‑art