Job Details: Job Description: The Physical Design Engineer (EM/IR Closure Engineer) is a hands-on individual contributor responsible for block-level and subsystem-level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Qualcomms Silicon Validation team is part of the central SoC digital hardware organization responsible for the overall quality of
Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication
IBM in Mexico is seeking a candidate for a design and verification role. You will be responsible for various aspects of electronic design, including logic, signal integrity, and thermal analysis. The ideal candidate will possess strong
Link-Worldwide is seeking a College Grad for a role in CPU development in Guadalajara, Mexico. Youll work on the E-Core CPU team, developing RTL implementations and new architecture capabilities aimed at enriching the future of computing. Responsibilities include
Link-Worldwide is seeking an FPGA/Emulation Engineer in Mexico to drive the development of innovative FPGA and emulation solutions. You will optimize RTL development and enhance usability for pre-silicon verification and validation. Successful candidates will have a Bachelor’s in relevant
ASSA ABLOY Global Solutions is seeking a Product Owner for their Fixed Infrastructure division. This role involves the product ownership of real-time location services (RTLS) hardware. The candidate will orchestrate multiple technology integrations and ensure development teams meet
Link-Worldwide is seeking a Logic Design Engineer to join their E-Core development group in Guadalajara, Mexico. You will focus on implementing RTL code for Intels next-generation CPU IP, ensuring high-quality design while collaborating across multiple sites. Ideal candidates
Material Flow & Storage Optimization Collaborate with cross‐functional teams including Production, Logistics, Engineering, and Purchasing to align material flow systems with business goals and production scheduling requirements. Identify bottlenecks and inefficiencies in current material flow processes
Job Description The Advanced Manufacturing Engineering Specialist will lead and oversee multiple complex projects focused on optimizing material flow, material storage, and advanced manufacturing processes across multi‐site operations. The specialist will interact directly with Design Engineering,
Overview This position is to work with a general leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the
Job Description Summary : Why this roleImpact: Your designs power mission-critical aerospace systems—your decisions directly influence customer outcomes.Growth: Lead initiatives, mentor others, and expand into value stream and model line efforts that accelerate your development.Collaboration: Work across
Company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive
CompanyQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob AreaEngineering Group, Engineering Group ASICS EngineeringGeneral SummaryAs a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT marketsResponsibilitiesThe candidate
We are looking for motivated engineers with Static timing analysis skill; good knowledge on timing convergence and corner definition in advanced tech nodes. If you have expertise in this area and are excited by driving leading
Roles & ResponsibilitiesOwn the E2E bare metal framework validation of Qualcomm mobile/ server/ compute SoC clock and power architecturesValidation planning – understand design changes, visualize standalone and system level test requirements and scenariosTest plan development – clearly
OverviewThis position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered
Company :QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area :Engineering Group, Engineering Group ASICS Engineering General Summary : As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile,
Tech IP Library Characterization EngineerTipo de empleo: PermanentTipo jornada: Full-timeFecha de publicación: Identificador oferta: *This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms