Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:Engineering Services Group, Engineering Services Group Mask Layout Design General Summary: - Develop block level layouts of advanced node custom Mixed-Signal analog IP designs for Smartphones, and
SwiftCruit is seeking candidates for a critical role in developing and supporting CAD software for product and process development in Mexico, Jalisco. This position requires strong experience in design automation and analog layout, along with a
Link-Worldwide in Tijuana, Baja California is seeking a CAD Engineer for PDK development. This role involves collaborating with the engineering community to develop tools for schematic and layout design, circuit simulation, and more. Preferred qualifications include experience
Job Overview In this highly cross functional role, you will be part of the General Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a lead of our
Link-Worldwide in Tijuana seeks a seasoned PDK expert to lead the CAD team in developing and supporting custom tools for various technology nodes. The role emphasizes collaboration with engineering to enhance design methodologies and ensure the integration
Link-Worldwide in Tijuana, Baja California is seeking a CAD Engineer for PDK development. You will collaborate with the engineering community to develop innovative tools for schematic and layout design, as well as circuit simulation. The ideal candidate
Link-Worldwide in Tijuana seeks an experienced lead for their CAD team, focusing on PDK development across Custom, Analog, and RF technologies. Candidates should have at least 10 years of experience in a hands-on PDK role, expertise in the
Job Description Develop block level layouts of advanced node custom Mixed‐Signal analog IP designs for Smartphones, and other wireless consumer electronic devices. Create, verify, and revise IP designs utilizing effective analog layout principals, such as device
CompanyQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob AreaEngineering Group, Engineering Group ASICS EngineeringGeneral SummaryAs a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT marketsResponsibilitiesThe candidate
JR Sr Engineer/Layout Engineer, Memory CAD, GuadalajaraCAD Engineer4Relocation Level:TBDResponsibilities- Develop, maintain, and support CAD software for product and process development. - Build and validate P‐cells, utilities, and automation scripts for layout and verification tasks. - Design
Company :QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area :Engineering Group, Engineering Group ASICS Engineering General Summary : As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile,
Overview Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.
We are looking for a highly motivated SRAM Mask Layout Designer to join our custom memory design team. This entry-level position offers an opportunity to work on cutting-edge semiconductor technologies and gain hands-on experience in physical
This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the
Overview Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.
Company: General Summary Responsibilities Develop block-level layouts of advanced‑node custom Mixed‑Signal analog IP designs for smartphones and other wireless consumer electronic devices. Maintain the layout database using Design Management software. Engage with the engineering design team
Company & Job Area QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA – Engineering Group, ASICS Engineering Job Summary Design and develop physical layouts for logic standard cells using industry-standard computer-aided design (CAD) tools, such as
Job Description Assist in creating physical layouts for SRAM and custom memory blocks using industry-standard CAD tools (e.g., Cadence Virtuoso). Perform layout verification including DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC. Collaborate with
This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the
Responsibilities Work with physical design, CAD, IP, and Design Technology teams on timing closure, flow script/tool development and validation. Responsible for Spice simulations (Hspice / Prime Sim / Finesim / AFS / Spectre) for PVT corners