# Sr Engineer, Memory CAD, Guadalajara Tlaquepaque, Jalisco, Mexico Apply Now Find out how well you match with this job Job IDJR85768 Our vision is to transform how the world uses information to enrich life for
Overview Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.
Req ID: JR86164 Sr Engineer, Memory CAD, Guadalajara Responsibilities Provide day-to-day support for CAD tools, flows, and collateral, ensuring they meet the needs of HBM design teams at the Guadalajara Design Center. Collaborate closely with HBM
Job Description Summary : As an Advanced Digital Design Engineer, you will be at the forefront of designing cutting-edge embedded systems for the future of flight avionics devices, adhering to DO-254 standards for New Product Introductions
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Senior Test Engineer must have the ability to be part of a focused, high-energy team
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Senior Test Engineer will be part of a focused, high-energy team that works collaboratively in
# Sr Engineer, Memory CAD, GuadalajaraTlaquepaque, Jalisco, MexicoApply NowFind out how well you match with this jobJob IDJR85768 Our vision is to transform how the world uses information to enrich life for *all*. Micron Technology is
In this dynamic role, you will collaborate with lead design engineers on board-level circuit design, integration, verification, and documentation of state-of-the-art aerospace processors and FPGA assemblies. This position combines some leadership with hands-on technical work, requiring
Job Description Summary : Role Summary Roles and Responsibilities - Design processor and/or FPGA assembles including design, schematic capture, component placement, layout constrains, PWB stackup, layout review/approval. - Conduct board brining up, integration, and verification activities.