We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
We Are :At Synopsys, we drive the innovations that shape the way we live and connect.Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.We lead in chip design, verification,
# Senior Engineer - CMOS & Metallization Test Structure Design and LayoutTlaquepaque, Jalisco, MexicoApply NowFind out how well you match with this jobJob IDJR Our vision is to transform how the world uses information to enrich
Req ID: JR New College Grad - Memory Cell Test Structure Design and LayoutOur vision is to transform how the world uses information to enrich life for all.Micron Technology is a world leader in innovating memory
Job Details Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be
Opportunity OverviewField Application Engineer in ATE (Automated Test Equipment) to develop imaginative, thorough, and practical application solutions.Develop, debug, and deploy automated test solutions on Teradyne ATE platforms for Digital, Power Management, System‐on‐Chip (SoC), Mixed‐Signal, and RF
Test Engineering Mgmt 3Educationindustrial engineering, communications and electronics or similarExperience5 - 8 yearsSkillsOffice suite (Word, Excel), Google Docs, MacrosAdvanced Internet Browser, Minitab, CAD viewersElectrical Circuit SoftwareKnowledgeKnowledge of failure analysis, electrical, physical, and physicochemical testing applied to
Link-Worldwide is seeking a Technical Engineering Intern in Guadalajara, Jalisco, Mexico. The role involves supporting NXP Engineers in various activities, including energy consumption characterization, demo development, and customer support. Ideal candidates will be students pursuing a Bachelor
Business Unit DescriptionNXPs Security & Connectivity business unit offers best-in-class security, contactless performance and the most complete solutions to produce unmatched mobile and Internet of Things (IoT) solutions.Department DescriptionScope of Responsibilities/ExpectationsYou will report to the MCU
You will report to the MPU Systems Applications Manager. in Guadalajara, Jalisco Mexico. Working as a Technical engineering Intern. The primary role is to provide support to NXP Engineers on many activities such as: energy consumption
Link-Worldwide in Guadalajara, Jalisco, is seeking a Technical Engineering Intern to support NXP Engineers. The primary responsibilities include energy consumption characterization, demo development, and debugging activities.The ideal candidate should be enrolled in a local university program partnered
We are looking for a person focused on mathematical models of mechanical characterization, with experience at the intersection of applied mathematics and materials. The work centers on modeling the mechanical behavior of polymeric films and multilayer structures,
Welcome! . Memory Validation Intern page is loaded# Memory Validation Internlocations: Mexico, Guadalajaratime type: Full timeposted on: Posted Todayjob requisition id: JR *# Job Details: # Job Description:This position requires candidates to upload a resume in
Our vision is to transform how the world uses information to enrich life for _all_ . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence,
Link-Worldwide, located in Mexico, Jalisco, Región Centro, seeks an experienced engineer with over 12 years in power management and circuit testing. Youll provide technical support to customers and lead new product development efforts. The ideal candidate
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JR88115 Senior Engineer - CMOS & Metallization Test Structure Design and Layout Relocation Level TBD Responsibilities Support process development activities through memory cell-based test structure solutions by actively engaging with Process Integration, Product and Design, Electrical
Req ID: JR96245 – New College Graduate – CMOS & Metallization Test Structure Design and Layout Semiconductor Design Engineer 2 Relocation Level: TBD Responsibilities Support process development activities through memory cell‑based test structure solutions by actively
As a Scribe Array Design Engineer, you will design and validate memory cell & support circuitry‑based test structures, manage design revisions, and partner with cross‑functional teams to support process development and manufacturing integration. Responsibilities Support process