Support emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware, bootloaders,
A leading tech company is looking for a CPU Design Engineer in Mexico, Jalisco, Región Centro. This role involves designing and implementing high-performance execution units in CPUs, working on microarchitecture, and collaborating with teams to meet
A leading tech company in Mexico is seeking a Senior CPU Design Engineer to design and implement high-performance execution units in CPU. This role involves optimizing for power, performance, and area (PPA). You will collaborate with
A technology company in Mexico, Jalisco is looking for a Power Management Architect to define system-level power management architecture and support silicon bring-up. The ideal candidate will have over 7 years of experience in SoC or
A leading technology firm in Mexico is seeking a Formal Verification Engineer to leverage advanced techniques ensuring the performance of RISC-V cores. This role involves collaborating closely with architects and RTL engineers to develop innovative verification
We are seeking a CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You will
Create and utilize cutting-edge tools and methodologies to detect, analyze, and resolve digital logic bugs in advanced CPU designs. Develop and implement verification methodologies that enhance design correctness, streamlining verification cycles for improved efficiency. Manage and
Define system-level power management architecture and operating modes Define CPU and cluster power states and their coordination mechanisms Define reset flow architecture, including cold and warm reset sequencing and reset-power state interactions Define PM policies, sequencing,
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver
Responsibilities Lead emulation bring-up of CPU RTL on hardware emulation platforms, including design partitioning, clock domain handling, and memory/IO modeling. Develop and maintain testbench infrastructure, C/C++ DPI-based transactors, and speed bridges enabling emulation-based execution of firmware,
A technology company is seeking a Physical Design Engineer in Guadalajara, Mexico, to optimize CPU power, performance, and area. Responsibilities include managing physical implementation from RTL to GDSII, working with RTL designers on timing and power
We are seeking a Formal Verification Engineer to join our team. In this role, you will leverage advanced formal verification techniques to ensure the correctness and performance of high-end RISC‑V cores. You will collaborate closely with
We are seeking a Senior CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You